gpio.h

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/*
 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _HARDWARE_GPIO_H
#define _HARDWARE_GPIO_H
 
#include "pico.h"
#include "hardware/structs/sio.h"
#include "hardware/structs/padsbank0.h"
#include "hardware/structs/iobank0.h"
#include "hardware/irq.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_GPIO, Enable/disable assertions in the GPIO module, type=bool, default=0, group=hardware_gpio
#ifndef PARAM_ASSERTIONS_ENABLED_GPIO
#define PARAM_ASSERTIONS_ENABLED_GPIO 0
#endif
 
enum gpio_function {
    GPIO_FUNC_XIP = 0,
    GPIO_FUNC_SPI = 1,
    GPIO_FUNC_UART = 2,
    GPIO_FUNC_I2C = 3,
    GPIO_FUNC_PWM = 4,
    GPIO_FUNC_SIO = 5,
    GPIO_FUNC_PIO0 = 6,
    GPIO_FUNC_PIO1 = 7,
    GPIO_FUNC_GPCK = 8,
    GPIO_FUNC_USB = 9,
    GPIO_FUNC_NULL = 0x1f,
};
 
#define GPIO_OUT 1
#define GPIO_IN 0
 
enum gpio_irq_level {
    GPIO_IRQ_LEVEL_LOW = 0x1u,
    GPIO_IRQ_LEVEL_HIGH = 0x2u,
    GPIO_IRQ_EDGE_FALL = 0x4u,
    GPIO_IRQ_EDGE_RISE = 0x8u,
};
 
typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t event_mask);
 
enum gpio_override {
    GPIO_OVERRIDE_NORMAL = 0,      
    GPIO_OVERRIDE_INVERT = 1,      
    GPIO_OVERRIDE_LOW = 2,         
    GPIO_OVERRIDE_HIGH = 3,        
};
 
enum gpio_slew_rate {
    GPIO_SLEW_RATE_SLOW = 0,  
    GPIO_SLEW_RATE_FAST = 1   
};
 
enum gpio_drive_strength {
    GPIO_DRIVE_STRENGTH_2MA = 0, 
    GPIO_DRIVE_STRENGTH_4MA = 1, 
    GPIO_DRIVE_STRENGTH_8MA = 2, 
    GPIO_DRIVE_STRENGTH_12MA = 3 
};
 
static inline void check_gpio_param(__unused uint gpio) {
    invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
}
 
// ----------------------------------------------------------------------------
// Pad Controls + IO Muxing
// ----------------------------------------------------------------------------
// Declarations for gpio.c
 
void gpio_set_function(uint gpio, enum gpio_function fn);
 
enum gpio_function gpio_get_function(uint gpio);
 
void gpio_set_pulls(uint gpio, bool up, bool down);
 
static inline void gpio_pull_up(uint gpio) {
    gpio_set_pulls(gpio, true, false);
}
 
static inline bool gpio_is_pulled_up(uint gpio) {
    return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0;
}
 
static inline void gpio_pull_down(uint gpio) {
    gpio_set_pulls(gpio, false, true);
}
 
static inline bool gpio_is_pulled_down(uint gpio) {
    return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0;
}
 
static inline void gpio_disable_pulls(uint gpio) {
    gpio_set_pulls(gpio, false, false);
}
 
void gpio_set_irqover(uint gpio, uint value);
 
void gpio_set_outover(uint gpio, uint value);
 
void gpio_set_inover(uint gpio, uint value);
 
void gpio_set_oeover(uint gpio, uint value);
 
void gpio_set_input_enabled(uint gpio, bool enabled);
 
void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
 
bool gpio_is_input_hysteresis_enabled(uint gpio);
 
 
void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
 
enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
 
void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
 
enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
 
void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
 
// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, the irq priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio
#ifndef GPIO_IRQ_CALLBACK_ORDER_PRIORITY
#define GPIO_IRQ_CALLBACK_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY
#endif
 
// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, the irq priority order of raw IRQ handlers if the priortiy is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio
#ifndef GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
#define GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
#endif
 
void gpio_set_irq_callback(gpio_irq_callback_t callback);
 
void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_callback_t callback);
 
void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
 
static inline uint32_t gpio_get_irq_event_mask(uint gpio) {
    check_gpio_param(gpio);
    io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
                                      &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
    io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u];
    return (*status_reg >> (4 * (gpio & 7u))) & 0xfu;
}
 
void gpio_acknowledge_irq(uint gpio, uint32_t event_mask);
 
void gpio_add_raw_irq_handler_with_order_priority_masked(uint gpio_mask, irq_handler_t handler, uint8_t order_priority);
 
static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority) {
    check_gpio_param(gpio);
    gpio_add_raw_irq_handler_with_order_priority_masked(1u << gpio, handler, order_priority);
}
 
void gpio_add_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler);
 
static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) {
    check_gpio_param(gpio);
    gpio_add_raw_irq_handler_masked(1u << gpio, handler);
}
 
void gpio_remove_raw_irq_handler_masked(uint gpio_mask, irq_handler_t handler);
 
static inline void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler) {
    check_gpio_param(gpio);
    gpio_remove_raw_irq_handler_masked(1u << gpio, handler);
}
 
void gpio_init(uint gpio);
 
void gpio_deinit(uint gpio);
 
void gpio_init_mask(uint gpio_mask);
// ----------------------------------------------------------------------------
// Input
// ----------------------------------------------------------------------------
 
static inline bool gpio_get(uint gpio) {
    return !!((1ul << gpio) & sio_hw->gpio_in);
}
 
static inline uint32_t gpio_get_all(void) {
    return sio_hw->gpio_in;
}
 
// ----------------------------------------------------------------------------
// Output
// ----------------------------------------------------------------------------
 
static inline void gpio_set_mask(uint32_t mask) {
    sio_hw->gpio_set = mask;
}
 
static inline void gpio_clr_mask(uint32_t mask) {
    sio_hw->gpio_clr = mask;
}
 
static inline void gpio_xor_mask(uint32_t mask) {
    sio_hw->gpio_togl = mask;
}
 
static inline void gpio_put_masked(uint32_t mask, uint32_t value) {
    sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask;
}
 
static inline void gpio_put_all(uint32_t value) {
    sio_hw->gpio_out = value;
}
 
static inline void gpio_put(uint gpio, bool value) {
    uint32_t mask = 1ul << gpio;
    if (value)
        gpio_set_mask(mask);
    else
        gpio_clr_mask(mask);
}
 
static inline bool gpio_get_out_level(uint gpio) {
    return !!(sio_hw->gpio_out & (1u << gpio));
}
 
// ----------------------------------------------------------------------------
// Direction
// ----------------------------------------------------------------------------
 
static inline void gpio_set_dir_out_masked(uint32_t mask) {
    sio_hw->gpio_oe_set = mask;
}
 
static inline void gpio_set_dir_in_masked(uint32_t mask) {
    sio_hw->gpio_oe_clr = mask;
}
 
static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
    sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask;
}
 
static inline void gpio_set_dir_all_bits(uint32_t values) {
    sio_hw->gpio_oe = values;
}
 
static inline void gpio_set_dir(uint gpio, bool out) {
    uint32_t mask = 1ul << gpio;
    if (out)
        gpio_set_dir_out_masked(mask);
    else
        gpio_set_dir_in_masked(mask);
}
 
static inline bool gpio_is_dir_out(uint gpio) {
    return !!(sio_hw->gpio_oe & (1u << (gpio)));
}
 
static inline uint gpio_get_dir(uint gpio) {
    return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway
}
 
extern void gpio_debug_pins_init(void);
 
#ifdef __cplusplus
}
#endif
 
 
// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio
#ifndef PICO_DEBUG_PIN_BASE
#define PICO_DEBUG_PIN_BASE 19u
#endif
 
// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio
#ifndef PICO_DEBUG_PIN_COUNT
#define PICO_DEBUG_PIN_COUNT 3u
#endif
 
#ifndef __cplusplus
// note these two macros may only be used once per and only apply per compilation unit (hence the CU_)
#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins;
#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x);
#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p))
#else
#define CU_REGISTER_DEBUG_PINS(p...) \
    enum DEBUG_PIN_TYPE { _none = 0, p }; \
    template <enum DEBUG_PIN_TYPE> class __debug_pin_settings { \
        public: \
            static inline bool enabled() { return false; } \
    };
#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings<x>::enabled() { return true; };
#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings<p>::enabled())
#endif
#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
#define DEBUG_PINS_CLR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_clr_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
#define DEBUG_PINS_XOR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_xor_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
 
#endif // _GPIO_H_