7 #ifndef _HARDWARE_PWM_H
8 #define _HARDWARE_PWM_H
11 #include "hardware/structs/pwm.h"
12 #include "hardware/regs/dreq.h"
19 #ifndef PARAM_ASSERTIONS_ENABLED_PWM
20 #define PARAM_ASSERTIONS_ENABLED_PWM 0
69 static inline void check_slice_num_param(__unused uint slice_num) {
70 valid_params_if(PWM, slice_num < NUM_PWM_SLICES);
79 valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
80 return (gpio >> 1u) & 7u;
91 valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
105 c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS)
106 | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
120 valid_params_if(PWM, div >= 1.f && div < 256.f);
121 c->div = (uint32_t)(div * (
float)(1u << PWM_CH0_DIV_INT_LSB));
136 valid_params_if(PWM, integer >= 1);
137 valid_params_if(PWM, fract < 16);
138 c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
152 valid_params_if(PWM, div >= 1 && div < 256);
171 c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS)
172 | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB);
183 c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS))
184 | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB));
211 check_slice_num_param(slice_num);
212 pwm_hw->slice[slice_num].csr = 0;
214 pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET;
215 pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET;
216 pwm_hw->slice[slice_num].top = c->top;
217 pwm_hw->slice[slice_num].div = c->div;
218 pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB);
255 check_slice_num_param(slice_num);
256 pwm_hw->slice[slice_num].top = wrap;
275 check_slice_num_param(slice_num);
277 &pwm_hw->slice[slice_num].cc,
278 ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB),
279 chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS
299 check_slice_num_param(slice_num);
300 pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB);
322 valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
335 check_slice_num_param(slice_num);
336 return (uint16_t)(pwm_hw->slice[slice_num].ctr);
349 check_slice_num_param(slice_num);
350 pwm_hw->slice[slice_num].ctr = c;
363 check_slice_num_param(slice_num);
364 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS);
365 while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) {
380 check_slice_num_param(slice_num);
381 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS);
382 while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) {
397 check_slice_num_param(slice_num);
398 valid_params_if(PWM, integer >= 1);
399 valid_params_if(PWM, fract < 16);
400 pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
412 check_slice_num_param(slice_num);
413 valid_params_if(PWM, divider >= 1.f && divider < 256.f);
414 uint8_t i = (uint8_t)divider;
415 uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
427 check_slice_num_param(slice_num);
428 hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB,
429 PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS);
440 check_slice_num_param(slice_num);
445 hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS);
458 check_slice_num_param(slice_num);
459 hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS);
489 check_slice_num_param(slice_num);
490 hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS);
511 check_slice_num_param(slice_num);
528 valid_params_if(PWM, slice_mask < 256);
542 pwm_hw->intr = 1u << slice_num;
560 pwm_hw->intf = 1u << slice_num;
569 static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1,
"");
570 static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7,
"");
571 check_slice_num_param(slice_num);
572 return DREQ_PWM_WRAP0 + slice_num;